A massive data traffic increase has been witnessed recently in data centers which, in turn, has forced interconnect link-speeds from lower speeds (e.g. 10-28 Gbps, etc.) to significantly higher speeds (e.g. 56 Gbps and up, etc.). Based on such demand, a throughput of interconnects [e.g. serializer/deserializer (SerDes), etc.] has been increased by at least a factor of two, and possibly higher.
This, in turn, has resulted in a variety of technical issues. For example, the precision of various interconnect link components must be particularly increased. In the context of noise cancellation, for instance, delay circuits may serve to appropriately time a feedback of input signals for the purpose of noise cancellation, etc. In such context, a delay of such delay circuits must be increasingly accurate (in duration) so that proper noise cancellation may be afforded.